The present invention is directed generally to memory systems for use in data processing equipment, and more particularly to apparatus for preventing excessive power consumption by the memory system.
Recent advances in very large-scale (VLSI) integrated circuitry fabrication has resulted in memory elements in the form of integrated circuit "chips" capable of storing large amounts of digital data. For example, there is now available on the market today VLSI memory element chips (typically, in the form of dynamic random access memory (DRAM) capable of storing one megabits (1,048,576), four megabits (4,194,304), and even sixteen megabits (16,777,216) of digital information. Typically, these memory element chips are organized to store N words by one bit. They are often used in multiples of M chips to form an array that provides N words by M bits of storage.
It is often advantageous to organize memory systems formed from such memory elements on a page basis; that is, contiguous groups of memory locations form one page, usually organized on a row address boundary that is in turn established by the memory element used. Memory accesses to different memory locations within each page are accompanied by column address strobes which signify presence of a memory location address at memory address inputs of the elements. A memory access to a different page of memory will cause occurrence of both a row address strobe signal and the column address strobe signal.
It has been discovered that, at high speed operation, excessive power consumption can occur in memory systems implemented using such VLSI memory elements, particularly when successive, back-to-back memory operations to different pages are performed. Successive back-to-back different page writes will tend to cause a charge build-up from the resulting string of row address strobes needed to make such different page writes. This string of row address strobes will tend to result in an increased current draw. Thus, it is believed that the worst-case power consumption situation will occur when successive different back-to-back write operations are performed.
This presents a good news--bad news situation. The good news is that multiple different page back-to-back write operations are believed to be infrequent. The bad news is that there is the possibility that a situation will arise, however infrequent, resulting in multiple back-to-back different page write operations. This, in turn, can cause the memory system to consume power beyond a power supply system's capability, resulting in a power shut-down to protect the system.
One solution to the problem can be to provide power supply systems designed to handle the excess power consumed during these infrequent back-to-back different page writes. However, this solution results in heavier, bulkier, and more expensive power supplies. Further, in the event that an existing data processing system is to be upgraded with more and newer memory of the type discussed above, it may not be an easy task to also upgrade the power supply capability without incurring undue cost.
There is a more elegant solution.